EV4101【PDF 7/68 页】32-bit Microprocessor that Executes MIPS

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TinyRISC

EV4101 Microprocessor Reference Device Technical Summary

instructions. Standard MIPS-compiled code will run without change on

the TR4101. Code containing a mixture of MIPS I/II and MIPS16

executes without any prior setup of the core.

The TR4101’s instruction set includes a WAITI instruction that places the

TR4101 into a low-power stall condition until an interrupt is received. For

even greater power management, the EV4101 has an output pin that is

asserted during this time period, so that the system designer can stop

the entire system clock.

The MDU module is attached to the TR4101’s FlexLink interface. It is a

compact, medium-performance MIPS II compatible arithmetic engine.

The MDU module supports 13-cycle integer multiply and multiply

accumulate, and 34-cycle divide operation.

The DBX module is attached to the TR4101’s FlexLink interface. The

FlexLink interface allows a number of new instructions to be added to the

microprocessor’s default instruction set. The DBX module facilitates

debug support by allowing the programmer to insert instruction and data

access breakpoints.

The SerialICE port is a full-duplex, serial, receive and transmit port. It is

used with the SerialICE concept for downloading application software to

the TR4101 and for debugging. The SerialICE concept uses the

breakpoints in the DBX module when required in the debug session.

The BBCC is connected to the microprocessor using the CPU bus

(CBus). The BBCC is a basic bus interface unit that handles

instruction/data block refilling, cache control, load scheduling, and

streaming. It contains the four-deep write buffer. Connected to the BBCC

are a 16 Kbyte two-way set-associative I-cache and an 8 Kbyte direct-

mapped D-cache. The BBCC has an advanced method of streaming

data to the microprocessor. Anytime the cache is being refilled, the

microprocessor can use the data during the same cycle it is written to

the cache. The BBCC is programmable using a system configuration

There are two internal 16-bit timers that are included in the EV4101.

They are connected to the BBCC using the BBus interface. Each timer

has an output that can be either toggled or pulsed. Timer 1 can be

placed in a bus Watchdog Mode where a bus error is signalled on

excessively long transactions. When the Timer 1 is in Watchdog Mode,

the EV4101 detects a bus error when a transaction exceeds the count

length that is programmed into Timer 1.

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